1. Field of the Invention
This invention relates to a method for fabricating semiconductor device, and more particularly, to a method for fabricating an SOI semiconductor device.
2. Description of Related Art
A related art SOI device is disclosed in U.S. Pat. No. 6,110,769 issued to Jeong Hwan Son, titled "SOI (SILICON ON INSULATOR) DEVICE AND METHOD FOR FABRICATING THE SAME", which is shown in FIGS. 1A and 1B-1H. Refer to FIG. 1A, which is a cross-sectional view showing a structure of a conventional SOI device.
A buried oxide film 25 is formed on a semiconductor substrate 24. P and N-type heavily doped polysilicon layers 23a and 23b are formed on the buried oxide film 25 and isolated from each other by an isolation oxide film 26 formed on the buried oxide film 25. Buried oxide films 22a are formed in the p and N-type heavily doped polysilicon layers 23a and 23b to be spaced apart.
A P-type semiconductor layer 20b and a first active region are formed on the first buried oxide film 22a, spaced apart from the P-type heavily doped polysilicon layer 23a. A first oxide film 21 is formed between the P-type semiconductor layer 20b and the first active region.
An N-type semiconductor layer 20c and a second active region are formed on the first buried oxide film 22a, spaced apart from the N-type heavily doped. A first oxide film 21 is formed between the N-type semiconductor layer 20c and the second active region.
A gate oxide film 29 and a first gate electrode 30a are successively formed on the first active region on the P-type heavily doped polysilicon layer 23a. Source/drain regions 34a/34b are formed in the first active region at both sides of the first gate electrode 30a.
A gate oxide film 29 and a second gate electrode 30b are successively formed on the second active region on the N-type heavily doped polysilicon layer 23b. Source/drain region 32a/32b are formed in the second active region at both sides of the second gate electrode 30b.
Formed is an interlayer insulating film 35 having contact holes on the p and N-type semiconductor layers 20b and 20c and the source/drain regions 32a/32b and 34a/34b. Contact pads 36a and 36f and line layers 36b, 36c, 36d, and 36e are formed in the contact holes and on the interlayer insulating layer adjoining to the contact holes.
The first and second active regions are connected to the p and N-type semiconductor layers 20b and 20c through the p and N-type polysilicon layers 23a and 23b, respectively.
Refer to FIGS. 1B-1H, are cross-sectional views showing conventional process steps of a method for fabricating the SOI device as shown in FIG. 1A First refer to FIG. 1B, a first semiconductor substrate 20 is provided. The first substrate 20 is etched to form a plurality of trenches. An oxide film is deposited on the substrate 20 and the trenches. Subsequently, a CMP process is performed to form a first oxide film 21 filling the trenches.
Next, a first buried oxide film 22 is formed on the first semiconductor substrate 20 by CVD.
A photoresist film is formed on the first buried oxide film 22 and patterned to expose areas of the first buried oxide film 22. Using the patterned photoresist as a mask, the first buried oxide film 22 is removed to expose the first substrate 20. Next an undoped polysilicon layer is deposited on the first buried oxide film 22 and the first substrate 20. The undoped polysilicon layer is then etched-back forming a thick undoped polysilicon layer 23.
A second semiconductor substrate 24 is provided and a second buried oxide film 25 is deposited on the second substrate 24. Subsequently, the second buried oxide film 25 on the second substrate 24 and the undoped polysilicon layer 23 on the first substrate 20 are bonded together by undergoing a high temperature process
Refer to FIG. 1C. The first substrate 20 is polished until the first oxide film 21 using the first oxide film 21 as an etch stop. In order to form a trench isolation region, the semiconductor layer 20a between the first oxide film 21, the first buried oxide film 22, and the undoped polysilicon layer 23 are etched. An oxide film is deposited on the first oxide film 21, the semiconductor layer 20a, and the trench isolation region and then planarizing the oxide film to form an isolation oxide film 26.
Next, a photoresist film 27 covers the first oxide film 21, the semiconductor layer 20a and the isolation oxide film 26. The photoresist film 27 is patterned and removed to expose part of the isolation oxide film 26. Using the patterned photoresist film 27 as a mask, the undoped polysilicon layer 23 is injected with boron ions to create a P-type heavily doped polysilicon layer 23a.
Refer to FIG. 1D. Subsequently, another photoresist film 28 covers the first oxide film 21, the semiconductor layer 20a and the isolation oxide film 26 and patterned. The photoresist film 28 is then removed to expose part of the isolation oxide film that was covered by the photoresist film 27 in the previous step. Using the patterned photoresist film 28 as a mask, the undoped polysilicon layer 23a is injected with phosphorus ions to become an N-type heavily doped polysilicon layer 23b.
Refer to FIG. 1E. An oxide film and a silicon layer are deposited and etched. The result is a gate oxide film 29 and a first gate electrode 30a for an NMOS transistor and a gate oxide film 29 and a second gate electrode 30b for a PMOS transistor formed on the semiconductor layer 20a.
Refer to FIG. 1F. A photoresist film 31 is formed and patterned to expose the semiconductor layer 20a on both sides of the second gate electrode 30b and where the first gate electrode 30a is not formed. Using the patterned photoresist film 31 as a mask, the P-type semiconductor layer 20b is injected with P-type boron ions to form lightly doped source/drain regions 32a and 32b.
Refer to FIG. 1G. A photoresist film 33 is formed and patterned to expose the semiconductor layer 20a on both sides of the first gate electrode 30a and where the second gate electrode 30b is not formed. Using the patterned photoresist film 33 as a mask, the N-type semiconductor layer 20c is injected with N-type As ions to form lightly doped source/drain regions 34a and 34b.
Refer to FIG. 1H. Depositing and removing an insulating film 35 to expose areas of the P-type semiconductor layer 20b, the N-type semiconductor layer 20c, the P-type source/drain regions 32a and 32b and the N-type source/drain regions 34a and 34b and form contact holes. A conductive layer is formed to fill the contact holes. The conductive layer is etched to form contact pads 36a and 36f on the P-type and N-type semiconductor layers 20b and 20c and line layers 36b, 36c, 36d, 36e on the n and p source/drain regions 32a/32b and 34a/34b.
The conventional method for fabricating an SOI semiconductor device as described above comprises implanting P-type ions to form regions 20b, 32a, and 32b. Additionally, the conventional method requires implanting N-type ions to form regions 20c, 34a, and 34b. Since photoresist films are used as ion-implantation masks, two lithography mask steps and two ion implantation steps need to be performed, which increases the complexity of the fabrication process and the cost thereof.